AMD has announced plans to add native UCIe 1.1 connectivity to select Versal adaptive SoCs, enabling direct, high-bandwidth communication between the devices and specialized co-packaged chiplets. The first products to support the interface will be selected devices in the Versal RF Series, with production chiplets expected in the fourth quarter of 2027.
The new devices will support up to four UCIe-SP interfaces and two UCIe-AP interfaces, providing multi-terabit-per-second aggregate bandwidth inside the package. This will allow designers to connect Versal devices directly to specialized chiplets for RF data conversion, AI acceleration, CPU and GPU processing, communications, security and application-specific ASIC functions.
UCIe is designed to provide a standardized die-to-die interconnect for heterogeneous chiplet systems. Instead of developing a new large monolithic SoC for every application, system designers can combine proven silicon blocks within a single package, potentially reducing latency, power consumption, system size and development complexity while allowing greater reuse of existing IP.
The Versal RF Series combines high-resolution RF data converters, dedicated DSP functions, AI Engines and programmable logic. According to AMD, adding UCIe will extend that architecture into a modular platform capable of integrating additional specialized compute and RF functions within the same package.
The announcement reflects a wider semiconductor-industry shift toward heterogeneous integration and chiplet-based architectures, where different types of silicon can be optimized independently and then connected through standardized high-speed interfaces.
Source: AMD
Photo credit: AMD
