SK hynix has highlighted a new technology roadmap for co-packaged optics (CPO) published in Nature Electronics, outlining how optical interconnects could help overcome the growing bandwidth and energy limitations of electrical links in AI and high-performance computing systems. The review was developed with researchers from several leading institutions and looks beyond memory technology alone toward system-level AI infrastructure.
As AI processors and memory systems scale, moving data between compute resources is becoming increasingly difficult using conventional electrical interconnects. SK hynix notes that compute throughput has historically advanced much faster than interconnect bandwidth, creating what the company describes as a growing “bandwidth wall.”
The roadmap examines the evolution of CPO from 2D integration to 2.5D photonic-interposer architectures and ultimately 3D heterogeneous stacking. By placing optical engines closer to processors and memory, these architectures can shorten electrical paths while improving bandwidth, latency and energy efficiency.
One of the more forward-looking concepts described in the work is an optics-centric architecture in which photonic interposers directly connect pools of compute resources with pools of memory. Such an approach could extend optical connectivity beyond rack-level networking and increasingly into the package and memory subsystem itself.
The Nature Electronics review also identifies several major challenges that still need to be solved before CPO becomes a mainstream computing technology, including thermal management, manufacturing complexity and standardization.
For SK hynix, the work signals an expansion beyond its leadership in HBM toward a broader role in AI memory, advanced packaging and optical interconnect architecture, as system performance becomes increasingly dependent on how efficiently processors and memory communicate.
Source: SK hynix / Nature Electronics
Photo credit: SK hynix
