Leveraging years of stacked BSI sensor production, Tower’s wafer-scale 3D-IC technology unlocks integration of SiPho and EIC processes for emerging applications such as Co-Packaged Optics, including full support by Cadence design tools to the stacked platform technology
Tower Semiconductor (NASDAQ/TASE: TSEM), a leading foundry of high-value analog semiconductor solutions, today announced the expansion of its existing, mature 300mm wafer bonding technology, originally developed and in mass production for stacked BSI image sensors, to enable heterogeneous 3D-IC integration across its industry-leading Silicon Photonics (SiPho) and SiGe BiCMOS processes, including full support by Cadence design tools for the stacked platform technology. The new offering, represents a major step forward in extending wafer-scale 3D integration, requiring simultaneous use of multiple-PDKs, to new domains beyond image sensing, addressing the growing market demand for compact, high-performance systems for data center applications.
Building on years of high-volume stacked sensor production on 200mm and 300mm wafers, Tower’s wafer bonding technology enables stacking wafers (for example, SiPho (PIC – Photonic IC) and SiGe (EIC – Electronic IC)) to create fully integrated 3D-ICs at the wafer scale. This capability integrates application-specific functions from different process technologies into a single high-density chip, delivering greater functionality and performance in a smaller form factor. This wafer-scale 3D-IC technology supports emerging applications such as Co-Packaged Optics (CPO), which combines PICs and EICs, where compact, high-performance integration is essential.
“Our long-standing experience in high-volume wafer stacking for CIS technologies has laid the foundation for this next stage of 3D integration,” said Dr. Marco Racanelli, President, Tower Semiconductor. “With our advanced 300 mm wafer bonding process now supporting multiple wafer technologies on a single 3D-IC, we are enabling customers to achieve new levels of performance, functionality, and integration density needed for CPO.”
Tower has already successfully demonstrated the wafer bonding process’s precision alignment and reliability. Complementing the process technology, Tower has collaborated with Cadence Design Systems to extend their Virtuoso Studio Heterogeneous Integration flow – which allows co-simulation and co-verification of multiple process technologies within a unified design environment. This enhanced design enablement capability is now available for our customers to use as a reference flow.
“Tower Semiconductor and Cadence have joined forces to provide a comprehensive design flow for multi-technology stacked die,” said Dr. Samir Chaudhry, VP of Customer Design Enablement, Tower Semiconductor. “This enables designers to lay out, check connectivity, and fully simulate 3D-IC and wafer-bonded chips built from multiple technology platforms, all within a single Cadence design project. Compatible with Tower Semiconductor SiGe BiCMOS and SiPho PDKs, – the new 3D-IC design flow is now fully supported by both companies, greatly improving first-pass success on complex multi-technology die projects.”
“Cadence and Tower have successfully collaborated for over two decades, helping our mutual analog IC customers achieve first pass success with their complex designs”, said Ashutosh Mauskar, VP, Product Management for the Custom Design and System Design and Analysis products, Cadence. “The validation of the Heterogeneous Integration flow, which supports die-to-wafer and wafer-to-wafer applications for PIC/EIC sub-systems using Tower technology, means our mutual customers can count on a robust and unified technology flow to help them deliver quality products on time.”
This expansion reinforces Tower’s leadership in 3D-IC and heterogeneous integration, delivering advanced analog solutions that accelerate innovation across next-generation markets.
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