MIPS selects Imperas Reference Models for RISC-V Processor Verification

Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced with MIPS, Inc., the processor technology company focused on the commercialization of RISC-based processor architectures and IP cores, the continuation and extension to the long-standing relationship with simulation and verification support for RISC-V. Since 2010, MIPS has partnered with Imperas for proprietary simulation technology and reference models for both internal engineering and customer ISS solutions. As the design and verification team transitions to the RISC-V open ISA (Instruction Set Architecture), the Imperas reference models for RISC-V form the essential reference for the processor functional verification tasks.

The latest RISC-V verification ‘step-and-compare’ methodology can be used to verify an RTL processor implementation against the Imperas golden reference model encapsulated within a SystemVerilog environment. This covers asynchronous events and offers a seamless, time-saving transition to debug analysis when an issue is found. More details on test benches with Imperas RISC‑V verification reference models are available at www.imperas.com/riscv.

Since the main role of a central processor is to execute software, software plays a major role in the complete design cycle from the initial project concept to the detailed functional verification, and in the case of processor IP, beyond into the final SoC design and end application development. SoC developers select processor IP based on many factors, however, one of the key deliverables that supports the ease of use is a high-quality ISS to support software development. Since 2010, the MIPS core IP deliverables have included the Imperas based ISS, and as a consequence Imperas technology has helped to support many projects in applications such high-performance wireless communications, networking, automotive and AI applications, with major customers including MediaTek and Intel Mobileye.

“As the MIPS design and verification teams transition to RISC-V, we see a lot of benefits from adopting the open ISA specification,” said Don Smith, Director of Engineering at MIPS, Inc. “As an IP company, we have a significant focus on the quality and verification of our processor IP deliverables. Imperas are the leaders in RISC-V simulation and verification and, with more than a decade of collaboration, they are the obvious DV partner for MIPS and its new RISC-V offerings.”

“RISC-V is at the forefront of a hardware design renaissance in optimized processors,” said Itai Yarom, VP of Sales and Marketing at MIPS, Inc. “But, an ISA only provides the envelope of possibilities. The art and science of processor optimization requires complete feature exploration and verification, which are supported by the reference model simulation and verification technology from Imperas.”

“The Imperas simulation technology has two unique attributes, it models processors with the accuracy, control, and visibility required for functional DV and secondly, it can be integrated into all the main EDA verification environments.” said Simon Davidmann, CEO at Imperas Software Ltd. “Integrating our RISC-V reference models into a SystemVerilog UVM testbench supports the latest techniques for asynchronous events with ‘step-and-compare’, and provides a single environment to efficiently resolve issues. With this expanded partnership, we are thrilled to support the MIPS strategy for RISC-V.”

At CDNLive in Munich, Germany, May 6-8 2019, Intel Mobileye presented a technical paper, “Hybrid Virtual + Emulation SoC Platform for SW-Drivers Validation”, which highlighted the full Linux OS boot in 32 seconds instead of 2-3 hours on the non-hybrid emulation. This was followed by the Imperas presentation discussing hybrid emulation with Imperas reference models and Cadence Palladium for a MIPS-based SoC. These presentations (SVG02, SVG03) are available for download, with free Cadence registration, at this link.

In 2018, the announcement of the MIPS I7200 multi-threaded multicore processor included highlights from MediaTek for 5G compute performance and Imperas for simulators, virtual platforms, and debug and analysis solutions that help accelerate software development for multicore and multi-threaded processor configurations. The full release is available at this link.

Availability

The Imperas RISC-V reference models and processor verification IP are available now; more details are available at www.imperas.com/riscv.

The free riscvOVPsimPlus package, including several Architectural Validation test suites and support for instruction coverage analysis, are now available on OVPworld at www.OVPworld.org/riscvOVPsimPlus.

RISC-V Summit 2021

The RISC-V Summit and DAC are co-located for 2021, running December 6-8 in San Francisco, CA.

Imperas is a Diamond Sponsor for the RISC-V Summit 2021; more details on all the keynotes, talks and to request a demo are available at this link.