, Formula E technology partnership with Audi and eMobility strategy
, Formula E technology partnership with Audi and eMobility strategy

Realizing 5G New Radio Massive MIMO Systems

The promise of Massive MIMO is so appealing that many operators do not want to wait for the 5G NR ecosystem to be ready and are considering deploying it on 4G equipment. However, its many benefits come with a set of challenges. The larger footprint, higher power and greater cost due to the multifold increase in system complexity in implementing Massive MIMO radios are major hurdles. Integrating the analog signal chain with digital front end (DFE) devices in the radio and a substantial increase in signal processing compute power are needed to overcome these challenges.

RFSoCs for 5G NR Massive MIMO

A 5G NR Massive MIMO implementation requires many active signal chains in the radio to connect to each antenna or a subset of antennas in the array. These active signal chains—which traditionally comprise data converters, filters, mixers, a power amplifier and a low noise amplifier—can lead to significant increases in power, form factor and costs. The large number of active signal chains in a Massive MIMO system and resulting increases in system power and footprint will make it difficult to realize commercially viable systems. The cost associated with moving data between the RF Front-Ends (RFFE) and the Digital Front End (DFE) is one of the key challenges that must be resolved for 5G—at the software, hardware, and system level.

Xilinx, for example, is addressing this challenge by replacing multiple ADCs and DACs along with other RF components on the board with direct RF-sampling data converters in its existing 16nm FinFET Multi-Processing SoC (MPSoC) family of products, which are designed and deployed for radio applications. This newly introduced SoC device family monolithically integrates RF sampling data converter technology, providing a wide-bandwidth platform for radio systems that is fully hardware- and software-programmable. Based on an ARM-class processing subsystem merged with FPGA programmable logic, the architecture features 12-bit, 4GSPS RF-sampling ADCs, and 14-bit, 6.4GSPS direct RF DACs, along with optimized digital down-conversion and up-conversion signal processing.

, Formula E technology partnership with Audi and eMobility strategy

Figure 1: Massive MIMO system implentation on RFSoC

Moving RF into the digital domain by integrating RF-sampling data converter technology not only overcomes the power, space, and cost challenges but also enables implementation of wide-bandwidth and multi-band systems. Analog RF in existing radio systems is typically designed to create relaxed discrete data converter specifications. These discrete data converters and analog RF components use older process nodes and are typically optimized for narrow bandwidths. The resulting analog RF solution is too large, power-hungry and costly for wide bandwidth MIMO and Massive MIMO radio systems. Integrating high-speed data converters, 6.4GSPS direct RF DACs and 4GSPS RF-sampling ADCs allows digital RF to be flexible, lower in power and wider in bandwidth, making it ideally suited for building MIMO and Massive MIMO systems with lower footprint, power and cost.

Massive MIMO system implementation on Zynq UltraScale+ RFSoC

The diagram below illustrates a typical Massive MIMO radio implementation using a Zynq® UltraScale+™ RFSoC device. The RFSoC has 33Gbps transceivers with hardened 100G Ethernet MAC/PCS and an RS-FEC that can be leveraged depending on the type of front-haul interface, be it the 25G CPRI or eCPRI protocol. Partial L1 functionality, such as iFFT/FFT transforms and associated physical random- access channel processing, can be moved to the radio for 50 percent bandwidth reduction (and associated cost and power savings) between the radio and baseband unit. RFSoC devices provide high-performance, low power DSP resources to implement the digital front end comprising digital up conversion, crest factor reduction, digital pre-distortion, passive intermodulation correction, equalization and down conversion. Appropriate interpolation filters on the transmit path and decimation filters on the receive path are used to run RF-DAC and RF-ADC at high clock frequencies, independent of the FPGA fabric frequencies, for better frequency planning. With careful frequency planning, multiple bands such as band 1 and band 3 for FDD Massive MIMO and band 38, 40, 41 and bands 42 and 43 for TDD Massive MIMO can be simultaneously supported, leveraging the wide bandwidth of the integrated RF signal chain.


Zynq UltraScale+ RFSoCs monolithically integrate high-speed, wide bandwidth RF-sampling data converters with a fabric rich in digital signal processing and compute resources to address the diverse multiband requirements of 5G NR and LTE-Advanced Pro MIMO and Massive MIMO radio system implementations. This technology addresses the challenges of Massive MIMO by significantly reducing system footprint, power and cost. The inherent programmability of Zynq UltraScale+ RFSoC devices and the ability to re-use existing solutions enables faster time to market while allowing simple field updates to comply with emerging standards and newer algorithms and PA technology.

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