Demand for linear RF power amplifiers (RFPAs) covering the frequency range 1.5 – 2.8 GHz is driving new design methods for broadband, linear, and highly efficient RFPAs operating in output back-off mode (OBO). Improving efficiency in power amplifiers has long been a challenge for designers, in part due to poor control of harmonic loading impedances. The difficulty of measuring waveforms at microwave frequencies makes it hard to determine if optimum waveshaping has been achieved. Broadband design adds an additional challenge when a harmonic of a lower operating frequency lies in the intended operating band. These inherent difficulties can be compounded by imprecise design techniques, leading to multiple time-consuming and expensive iterations.
In this article, a first-pass design flow is described that uses NI AWR Design Environment, specifically Microwave Office circuit design software, as well as a measurement technique for the input and output impedances of the matching networks prior to RFPA “turn-on.” Several approaches to the problems inherent in PA design are presented with an aim of minimizing uncertainty and achieving first-time success.
The effectiveness of this approach is demonstrated using a commercially available discrete 10 W gallium nitride (GaN) on silicon (SiC) packaged high-electron-mobility transistor (HEMT) using a 0.25 µm process (Qorvo T2G6000528) and a 20 mil RO4350B printed circuit board (PCB) dielectric. The fabricated RFPA achieved a peak power of >+40 dBm and a peak drain efficiency of >54 percent over its operating bandwidth. In back off-mode the RFPA achieved an un-corrected linearity of 30 dBc and drain efficiency ≥34 percent when driven with a coded orthogonal frequency-division multiplexing (COFDM) 2.5 MHz, 9.5 dB peak-to-average power ratio (PAPR) modulated signal in the 2.0 – 2.5 GHz band.
RFPA Design Flow
The initial design of the RFPA began with a thorough device/technology selection process, the purpose of which was to select a best candidate device against a specific set of criteria prior to the time-consuming tasks of load/source pull and network synthesis. Several candidate devices seemed acceptable on the basis of claimed frequency and power. In addition to the more common parameters such as Vds, gain, operating frequency range, and power rating, other more detailed device data such as Cds, Cgs, and transformation ratio were also carefully considered.
Optimal Load Impedance Extraction
Once a device was selected and a nonlinear model obtained, the optimal source and load impedances were determined. The required load impedances necessary to achieve maximum power, maximum efficiency, gain, or an acceptable trade-off between these performance metrics are frequency dependent and vary substantially over the operating bandwidth of a broadband design.
To determine the correct load impedance, a combination of load-pull plotting at the fundamental and harmonic frequencies, waveform engineering, or circuit design techniques based on shaping the transistor voltage and current waveforms, were performed in Microwave Office. It should be noted that using waveform engineering in determining any optimal impedance relies on having access to the intrinsic device nodes, in other words, across the intrinsic current generator of the device plane rather than at the package reference plane. Assuming the nonlinear model provides these nodes, then a waveform engineering approach enables the visual observation of voltage and current swing, clipping, and class of operation of the amplifier.
For this example, the load pull simulation was run at Vds = +28V, Idq = 90 mA across the operating band and the optimal power and efficiency impedances were extracted with the mid-band results shown in Figure 1. A target load region based on the overlap between the Pmax -1 dB and drain efficiency max (effmax) – 5 percent contours was defined. Clearly, the larger this target area is, the easier the matching problem becomes. In this case Pmax occurred on a tightly-packed, clockwise rotating locus over the operating bandwidth, which was helpful in the case of the broadband amplifier. Load pull was performed at the fundamental frequency due to the broadband nature of the RFPA and consequent difficulties in achieving the optimal harmonic terminations  without using TX zeros in the network . Load pull at the second harmonic was also performed and a region of high efficiency identified  that could be controlled in the network synthesis.
Figure 1: Fundamental load pull analysis from within Microwave Office showing contours at constant compression with Pmax ≥4 1dBm and Effmax ≥70 percent for min, mid, and max frequency points over the operating bandwidth. The boundary region is defined as the intersection of Pmax – 1 dB and Effmax – 5 percent, Zo reference = 50Ω
Narrowband RFPAs have the advantage of showing little variation of the optimal load impedance over their operating bandwidth and hence the task of network design is somewhat less complex. This is not to say that a low fractional bandwidth match is always trivial. Indeed an investigation of source and load impedances will reveal that for very high performance, the network fundamental impedance must often be precisely controlled to a single gamma point with significant sub-optimal performance penalties if the network locus ‘misses’ its target load impedance. Morever, precise control of harmonic termination impedances for F and F-1 classes and the complexity of the task increases beyond what is required for an average performing power amplifier design. However, in the case of a broadband amplifier, particularly one with high performance specifications, the realized network is required to control the impedance variation over a far larger fractional bandwidth. After defining optimal impedances and target areas, the load network was developed using a simplified real-frequency technique (SRFT)  to design the ideal lumped element network and then convert to distributed stepped impedance format  before performing electromagnetic (EM) simulation on the network. In this example, the EM results agreed closely with the predictions of circuit-based modelling, but for less conventional matching topologies this might not be the case. In general, EM simulation is seen as an important step in reducing uncertainty in the design flow.
One design technique is to represent the conjugate of the optimal impedance as that of a two-terminal generator (port 1), after which the matching network design can be viewed as a problem of reducing the mismatch loss that exists between this complex-valued load and a 50Ω termination over the amplifier’s operating bandwidth. This mismatch can, however, be evaluated at the 50Ω side (port 2) of the network as shown in Figure 2a.
Figure 2a: Load network loss and match as a function of frequency of the realized distributed load network.
As a passive network, the output matching circuit had an operating power gain < 1, equal to its efficiency as determined by internal dissipative loss only. The necessarily smaller transducer gain was the product of this efficiency with the effect of loss due to reflection at the input. These quantities are presented as percentage efficiencies in Figure 2b.
Figure 2b: Transducer power gain (GT) as a function of frequency to express load network efficiency of the realized distributed load network. Operational power gain (GP) is shown for comparison.
The transducer gain was evaluated for a generator whose impedance is the conjugate of the target load impedance to be seen by the device drain. Although the output was matched for compressed power and efficiency, not small reflection at the drain, the second factor was found to agree closely with the predicted reduction in compressed power due to imperfect realization of the target load impedance. Thus, the plotted transducer gain was a good measure of the overall quality of the output matching achieved.
A further analysis (Figure 2b) of the load network using transducer power gain (GT) as a measure of load network mismatch loss between the transistor and the purely real 50Ω termination was also considered. An efficiency figure for the load network was calculated as 96.6 percent at 2800 MHz, with close correlation to the value calculated from the return loss at the same frequency. For comparative purposes the operational power gain (GP), which considers purely ohmic loss in the network, was also calculated to have an efficiency of 97.7 percent. Although this dissipation loss does not directly include reflection losses, its value does depend on the termination impedances as these affect the distribution of current and voltage within the network, and hence the copper and dielectric losses respectively.
Achieving a broadband optimal match using this transistor was relatively straightforward for several reasons. Firstly, the transformation ratio is relatively low (about 2:1) over the operating bandwidth; secondly, the load impedance for optimal Pmax points were tightly packed, and thirdly, the optimal impedance varied with increasing frequency on a clockwise rotating locus. As commented above, the fairly low transformation ratio was a useful criterion favoring selection of this GaN device in a broadband RFPA application.
Control of the source impedance variation over operating bandwidth was achieved through the use of a bandpass filter network, which also has the advantage of reducing low frequency gain, where the transistor’s inherent gain is very high. This particular source impedance matching network is also responsible for assisting with the amplifier’s low frequency stability. The impedance transformation ratio of about 15:1 needs a more elaborate network. In general, although not used here, matching networks with a deliberate positive slope, or equalization, can conveniently be introduced in the source matching circuit.
Stability of the RFPA was achieved using a shunt connected series R – C pair adjacent to the input port followed by a series R. Although this was quite a severe approach, analysis showed the transistor to be potentially unstable in the operating band and therefore some gain was sacrificed in order to obtain unconditional stability from 1 MHz to >6 GHz where the transistor ceased to have gain (Fmax).
Waveform engineering  was also used to analyze the RFPA, using both the load-pull tuner and, more critically, the realized load network. Recent device models giving access to the voltage and current nodes at the intrinsic current generator plane allow accurate observation of both the V and I waveforms, as well as the dynamic load line (DLL), for analysis of clipping and the RFPA mode of operation, as well as the peak voltages and currents generated.
Prior to these nodes being available, the only simple option was to monitor waveforms at the package plane, which clearly has limitations due to the package parasitic effects. (Negation of the parasitic network was feasible, but only if topology and component values are known and their electrical impact removed through de-embedding during simulation). Although care had been taken to control the second harmonic load impedance, analysis of the waveforms, as shown in Figure 3, showed that third harmonic impedance was very favorable without further optimization.
These waveforms showed a peak voltage of <60 V and a peak current of <1500 mA at 1500 MHz, which were well within device ratings. What was more instructive in terms of the efficiency performance was the near-ideal Class F operation with the half-wave rectified current waveform exactly 180 ̊ out of phase with the voltage waveform and very little voltage/current overlap. Using a DLL (dynamic load line) analysis, the waveform was defined as three regions; Region A where Vmin and Imax, Region B where Vmax and Imin, and the transition region. Using this technique, the waveform was controlled successfully. Calculating over one period, it was found that the waveform remained in Region A or B for 63.8 percent of the time and the transition occupied only 36.2 percent.
Figure 3a: DLL using intrinsic V and I nodes at 1500 MHz CW stimulus. Regions A, B, and transition defined.
To validate the approach and its accuracy, the RFPA was fabricated on Rogers 4350B 20 mil dielectric (εr = 3.48). The circuit was mounted on a jig consisting of 3 pieces containing: the source network (INMAT), load network (OUTMAT), and a copper center section to mount the device which was required to have its source soldered down as shown in Fig. 4 (a).
Figure 3b: Intrinsic V and I waveforms using the same nodes with corresponding regions defined in shaded area. Power output is 10W
Prior to assembling the complete RFPA the impedances of the INMAT and OUTMAT circuits, as presented to the transistor tabs, were measured to correlate modelled vs measured datasets. The measured data shows an excellent agreement between modelled impedance and measured impedance over an extended bandwidth of 1000 – 3000MHz with no tuning, as shown in Fig. 4 (b). An additional measurement of the INMAT and OUTMAT was performed from 20MHz to 10GHz and still showed very good agreement between modelled and measured datasets as shown in Fig. 5. With the aid of such a demountable jig, the impedances seen by the device can be measured directly and accurately without using mechanically awkward probes that also introduce electrical parasitics, notably stray inductance at the attachment point. The jig is not the production version of the amplifier, but its use is seen as an important stage of the design flow which conforms to the theme of eliminating uncertainties at every possible stage of the design.
Figure 4: (a) Fabricated RFPA on jig showing individual INMAT and OUTMAT measurement jigs and copper center section, (b) Measured vs modelled INMAT and OUTMAT 1000 – 3000MHz.
Figure 5: Measured vs modelled INMAT and OUTMAT 1000- 10000MHz.
Small Signal Measurements
Initial small signal gain measurements were carried out using a drain bias of Vds = +28V and an Idq = 90mA. A high degree of correlation between measured and modelled gain and match was observed as shown in Fig. 6 with an input return loss of >7.5dB over the operating band. Additionally, the RFPA exhibited no instability under practical stability tests such as varying the drain rail voltage and using an external tuner to vary the source impedance seen by the device.
Figure 6: Comparison of modelled vs measured small signal gain and input return loss.
Large-Signal Measurements (Continuous Wave)
The large signal measurements were carried out using a drain bias of Vds = +28V and an Idq = 90 mA. A continuous wave (CW) signal source was fed into a driver amplifier prior to being fed into the amplifier under test. The RF input and RF output power measurements were corrected for any compression occurring in the driver stage. The three performance parameters measured were power gain, drain efficiency and power delivered to the load. In order to provide a reference these were all evaluated at the 3dB compression point. Modelled results showed a P3dBmax of 40.99 dBm, maximum drain efficiency of 63.2 percent, and a maximum gain of 16.41 dB. Measured results showed a maximum P3dB of 40.6 dBm, maximum drain efficiency of 59.1 percent, and a maximum gain of 15.7 dB. The results in Figure7 show a high degree of agreement between modelled and measured datasets. It should also be noted that the RFPA delivered ≥10 W down to 1300 MHz and up to 2900 MHz, extending its range to a fractional bandwidth (BW) of 76.2 percent.
Figure 7: Modelled vs measured large signal CW results.
To evaluate the efficiency in output back-off mode and the intermodulation sideband performance, a 2.5 MHz channel BW COFDM signal with 9.5 dB PAPR was used over the band 2.0 – 2.5 GHz. In single-ended form at +34.5 dBm output, the average efficiency was 34 – 35.9 percent, with a linearity of 30 dBc measured at fcenter +/-1.25 MHz as shown in Fig.8. Similar results were obtained in the band 1.805 – 1.88 GHz using a wideband code division multiple access (WCDMA) test signal with PAPR = 7.8 dB. A balanced version of this amplifier is under construction.
Fig.8 Intermodulation sideband performance measured using modulated test signal.
Including imperfect hybrids, it was predicted to have performance that achieves +37 dBm with an average efficiency of ~34 percent and a linearity of 30 dBc at fcenter +/- 1.25 MHz. The linearity performance could be improved through linearization techniques such as digital pre-distortion or envelop tracking. It is interesting to note that achieving a high-efficiency class of operation at signal peaks enables operation at greater peak compression, so the amplifier is operated at higher relative power over the whole signal dynamic range. Hence the efficiency and/or linearity is improved even on high PAPR signals.
This paper has presented a design for a broadband, linear, and efficient output back-off mode RFPA, emphasizing the importance of minimizing design uncertainties wherever possible. Using this approach, excellent agreement between the modelled and measured datasets has been proven and a first-pass design achieved.
The design methodology used four stages: device selection using qualitative and quantitative analysis, optimization in Microwave Office of load and source impedance matching networks using load/source pull, passive network synthesis (including EM verification), and waveform engineering using intrinsic voltage and current nodes. Together these techniques have proved to provide a systematic approach to designing the entire RFPA.
In addition, a measurement technique for fabricated source and load networks, enabling comparison of modelled and measured impedances at the transistor tabs, has been demonstrated using a three-piece jig. Passive network synthesis using an SRFT technique combined with analysis using mismatch loss and transducer power gain has produced a broadband match using relatively simple source and load impedance matching networks. The results indicate that this particular RFPA could be well suited to operate as a multipurpose driver or output stage.
The author would like to thank Andy Wallace of AWR Group, NI and Qorvo / Modelithics for the device model.
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