Xilinx, Arm, Cadence Design Systems, Inc. and TSMC today announced a collaboration to build the first Cache Coherent Interconnect for Accelerators (CCIX) test chip in TSMC 7nm FinFET process technology for delivery in 2018. The test chip aims to provide a silicon proof point to demonstrate the capabilities of CCIX in enabling multi-core high-performance Armֲ® CPUs working via a coherent fabric to off-chip FPGA accelerators.
“As we work to innovate on advanced technology for compute acceleration, we are excited about the results of this collaboration,” said Victor Peng, COO at Xilinx. “Our Virtex UltraScale+ HBM family is built using TSMC’s 3rd generation CoWoSֲ® technology, which is now the industry standard assembly for HBM integration and cache-coherent acceleration with CCIX.”
“With the surge in artificial intelligence and big data, we’re seeing increasing demand for more heterogeneous compute across more applications,” said Noel Hurley, vice president and general manager, Infrastructure Group, Arm. “The test chip will not only demonstrate how the latest Arm technology with coherent multichip accelerators can scale across the data center, but reinforces our commitment to solving the challenge of accessing data quickly and easily. This innovative and collaborative approach to coherent memory is a significant step forward in delivering high-performance, efficient data center platforms.”
“By building an ecosystem for high-performance computing with our collaboration partners, we will enable our customers to quickly deploy innovative new architectures at 7nm and other advanced nodes for these growing data center applications,” said Babu Mandava, senior vice president and general manager of the IP Group at Cadence. “The CCIX industry standard will help drive the next generation of interconnect that provides the high-performance cache coherency that the market is demanding.”
“Artificial intelligence and deep learning will significantly impact industries including media, consumer electronics and healthcare,” said Dr. Cliff Hou, TSMC vice president, Research & Development/Design and Technology Platform. “TSMC’s most advanced 7nm FinFET process technology provides high performance and low power benefits that satisfy distinct product requirements for High-Performance Computing (HPC) applications targeting these markets.”
The test chip will tape-out in early Q1 2018 with silicon availability expected in 2nd half 2018.