Imperas RISC-V Reference Model, Test suites and Verification IP for advanced ‘lock‑step‑compare’ Processor Verification including Asynchronous events and Coverage Analysis.
Oxford, United Kingdom, May 24th, 2022 — Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced that NSITEXE, Inc., a group company of the DENSO Corporation that develops and sells high-performance semiconductor IP for automotive applications, has selected ImperasDV™ for advanced RISC-V processor hardware design verification. This expands and extends the use of Imperas simulation technology, models, verification IP and tools by NSITEXE for the next generation of 64bit RISC‑V based designs featuring vector accelerators for AI (Artificial Intelligence) automotive applications with verification leading to the level required to achieve ISO 26262 ASIL D.
RISC-V is an open standard ISA (Instruction Set Architecture) that allows processor developers to optimize the configuration with both standard extensions and custom instructions. The recently ratified RISC-V Vector Extensions support the compute requirements for hardware accelerators for applications involving linear algebra, which is well suited for the emerging AI algorithms and workloads in advanced automotive applications.
ImperasDV is the integrated solution for RISC-V processor verification that provides an adaptable framework based on the open standard RVVI (RISC-V Verification Interface) that supports the core RTL verification with the Imperas reference model in a ‘lock-step-compare’ methodology in addition to test suites and other verification IP. ImperasDV covers the verification tasks for implementations that range from basic controllers through to advanced designs featuring vector extensions, privileged mode security protections, multi-hart, and custom extensions. In addition, the freedom of the open standard ISA of RISC-V is enabling advanced processor technology in many new application areas with developers exploring techniques such as superscalar, out-of-order execution, multi-threading, heterogeneous multi-core and processor arrays plus other new and creative approaches for the next generation of domain specific devices. ImperasDV complements the verification tasks for development teams at the forefront of processor exploration.
“The flexibility of the RISC-V ISA coupled with the performance of vector extensions is an ideal starting point for AI accelerators for automotive applications,” said Hideki Sugimoto, CTO of NSITEXE, Inc., a group company of DENSO Corporation. “To address the verification requirement for our next generation of processors, we have developed an optimized verification flow with ImperasDV that our design team set up with detailed configuration options to deliver on their comprehensive verification plans that provides the industry leading quality our customers expect.”
“The open ISA of RISC-V is enabling a new wave of processor design innovation across the spectrum of compute requirements in almost all market segments,” said Nobuyuki Ueyama, President of eSOL TRINITY Co., Ltd. “High quality processor verification is not a simple task, but the ease of use and configurable approach with RVVI offered by ImperasDV enables the eSOL TRINITY team to support the expert design teams at NSITEXE and other leading adopters of RISC-V in Japan.”
“The open standard ISA of RISC-V is enabling a fundamental shift in processor development, with developers able to explore and innovate solutions with optimized solutions for targeted applications,” said Simon Davidmann, CEO at Imperas Software Ltd. “The flexibility of RISC-V on the design side has a direct impact on the verification task, and since the value-added features are central to the development, we developed ImperasDV to be adaptable for all implementations to allows our customers and users to verify state-of-the-art designs independently. NSITEXE are pioneers in developing advanced RISC-V vector accelerators for AI, and we are pleased to see the Imperas technology and ImperasDV supporting the quality requirements for automotive applications.”
Availability
ImperasDV is available now, with more details available at Imperas.com/ImperasDV.
The ImperasDV RISC-V processor verification technology is already in active use with many leading customers, some of which have working silicon prototypes and are now working on 2nd generation designs. These customers, partners and users span the breadth of RISC-V adopters from open source to commercial; research to industrial; microcontrollers to high performance computing. A select sample of these include – Codasip, EM Microelectronics (Swatch), NSITEXE (Denso), Nvidia Networking (Mellanox), OpenHW Group, MIPS Technology, Seagate Technology, Silicon Labs, and Valtrix Systems, plus many others yet to be made public.
The open standard RVVI (RISC-V Verification Interface) provides the essential guidelines for the infrastructure around the processor testbench that supports the growing ecosystem of Verification IP for RISC-V processor verification. The new RVVI open standard and methodology, is based on an open specification (https://github.com/riscv-verification/RVVI) and can be adapted to any configuration permitted within the RISC-V specifications. In adopting the RVVI standard, developers can leverage all the common components off the shelf and explore additional options with reusable Verification IP across projects.
The free riscvOVPsimPlus package, including the Imperas RISC-V Reference Model, sample test suites and instruction coverage analysis, including updates for the latest RISC-V ratified specifications is also available on OVPworld at www.ovpworld.org/riscvOVPsimPlus.
