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Market-Driven Trends in Hardware Emulation

Five of the largest semiconductor vertical markets are combining to drive several of the widest industry trends: unending growth in design complexity and size, proliferation of peripherals, increase in computing power, surging I/O traffic activity, and a critical need to contain the otherwise escalating energy consumption. The cumulative effects of these trends impact dramatically the design verification landscape and foster widespread adoption of hardware emulation platforms.

The five verticals contributing to these trends are data center networking, communication/5G, autonomous driving (AD), storage, and artificial intelligence (AI) & machine learning (ML).

A brief history of hardware-assisted verification
According to the ESD Alliance, a SEMI Technology Community, the hardware-assisted verification (HAV) market has grown haltingly since 1995, lagging behind hardware description language (HDL) simulation with a gap exceeding $200 million for the entire 2000-2010 decade. Starting in 2011, a surge in HAV revenues closed the gap, only to reopen and widen again from 2014.

In 2018, a new reality reversed the gap in favor of HAV tools. The ESD Alliance reported a 2020 record revenue for HAV tools in the amount of $718 million. See Table # 1.

Table #1: Revenue trends for hardware-assisted verification show growth. (Image source: The ESD Alliance, a SEMI Technology Community)

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It is reasonable to assume that the drive to embrace hardware-assisted verification from the five critical markets will continue and accelerate in the foreseeable future.

Trends and verification challenges in data center networking, communication/5G, AD, AI/ML, and storage markets underline how leading-edge hardware emulators — the largest contributor to the HAV market —can address them. Power trends and power analysis are briefly discussed in the last section.

Data center networking

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Data center networking adds a host of verification challenges.
(Image source:
Siemens EDA)

Data center networking enjoyed explosive growth sustained by new applications, such as software-defined networking (SDN). Emerging protocols that include 5G, time-sensitive networking (TSN), and automotive internet played a role as well. All contribute to an expanded port count, now exceeding 256, increased port speeds approaching 800Gb/sec, enlarged bandwidth, and lowered latencies. The consequence is exploding design sizes into multi-billion equivalent gates, and daunting pre-silicon design verification due to shrinking time allocation to ensure that performance and power budgets are met.

Hardware Emulation for Networking

To meet the challenges, a leading-edge hardware emulator must possess three traits: platform, applications, and ecosystem.

As for the platform, its capacity must reach 15 billion gates with scalability starting at one billion gates, while maintaining consistent speed of execution across all configurations. It ought to support ternary content-addressable memories (TCAMs) natively to avoid cumbersome and inefficient modeling. Equally important, the communication channel between the test environment and the device under test (DUT) running in the emulator must exhibit wide bandwidth and low latency to accommodate the increasing number of ports.

As for applications, both in-circuit emulation (ICE) and virtual deployment are necessary. Deterministic debugging is a must for ICE, and a rich set of speed adapters is essential. For virtual mode, an expanded library of proven virtual solutions (such as VirtuaLAB Ethernet and VirtuaLAB PCIe from Siemens) is mandatory.

 

Communications and 5G
Two characteristics of the communication market, specifically 5G applications, stand out. First, a stream of about 50,000 5G patents in 2018 demonstrates deployment acceleration. Second, specialized semiconductor content is required to meet low power, performance, size, and latency, across a range of applications such as smart devices and cities, IoT edge products, virtual reality, digital industry applications, virtual reality, and autonomous driving vehicles.

Hardware Emulation for 5G

To address 5G design verification, a comprehensive, end-to-end suite of tools integrated in a flow that starts at the pre-silicon intellectual property (IP) level and proceeds all the way to the post-silicon test lab is a necessity.

Figure #2: A 5G end-to-end, pre- and post-silicon development and verification flow encompasses simulation, emulation, prototyping, unit testing, system integration, and post-silicon testing. (Image source: Siemens EDA)

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In a complete verification/validation cycle, the flow encompasses simulation, emulation, prototyping, unit testing, system integration, and post-silicon testing. Simulation is aimed at IP/block-level verification. Hardware emulation takes over from simulation to perform sub-system verification and, in combination with FPGA prototyping, verifies and validates the full system including software through tape-out. A well-integrated suite of emulation and prototyping platforms can share the same stimulus and verification setup from end to end.

Autonomous driving
AD designs involve several critical issues from safety and security concerns to avoid liabilities to big data processing that require massive communication between vehicle and cloud computing.

Verification challenges stem from the growing number of sensors that may exceed 50 various types, the increasing amount of software, now reaching 100 million lines of code, and the hardware and software complexity that must be validated together. This requires a vast amount of verification cycles to certify that an autonomous driving car is safe and secure.

Hardware Emulation for AD

Verification/validation of an AD controller must deal with sense, compute, and actuate. Sense collects sensory information to capture driving scenarios. Compute performs algorithmic processing of those scenarios to formulate a decision. Action acts on those decisions by sending commands to the engine, transmission, steering and braking system, calling for integration of several technologies. Hardware emulation computes the sensor data generated by a virtual environment like VECTOR CANoe, dSPACE, or Siemens Pre-Scan, and generates actions to be sent to actuate implementation via functional models for the engine and steering wheel, such as Siemens AMESim, and others.

Figure #3: An autonomous vehicle verification and validation environment must consider sense, compute, and actuate. (Image source: Siemens EDA)

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AI/ML
AI/ML designs record the largest transistor count driven by new architectures for computing, storage, and memory access. New architectures target specific applications, such as tensor processing unit (TPU), neural network processor (NNP), neural processing engine (NPE), as well as type of implementations, such as 2D, 3D stacking, chiplets, FPGA fabric, and custom AI logic. From the verification perspective, design capacity, design fabric, power analysis, and software stack validation are the four capabilities that must be handled. Hardware Emulation for AI/ML

Based on these design characteristics, an emulation platform must accommodate up to 15 billion gates, and compile designs at rates of several hundred million gates per hour for fast turnaround time (TAT) to find and fix a bug, recompile and rerun emulation. It must support a wide communication bandwidth between the host computer and the emulator to manage the intense traffic between the virtual test environment and the DUT. It ought to perform accurate power analysis and be able to execute customer software stacks dependent on the application.

Storage (SSD versus CSD)

Figure #4: Implementing a computational storage device can eliminate some bottlenecks to improve performance, lower power, and free up PCIe bandwidth.
(Image source: Siemens EDA)

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Three bottlenecks undermine the solid-state drive (SSD) adoption. First, the storage media consisting of NAND flash fabric endures finite life expectancy, wear leveling, the need for garbage collection, performance degradation over time, finicky reliability, and random latency. Second, the host computer interface’s bandwidth and latency do not meet SSD requirements to deliver its full potential. Third, the physics of data movement lower performance and power consumption targets, though some bottlenecks have been eliminated in the computational storage device (CSD).

In the SSD, a host computer issues a request for data to the storage drive. Storage sends the data to the computer and the computer writes the processed data back to storage. In the CSD, the host computer sends a request to a lightweight computer installed locally within the CSD. The local computer, instead of sending the data back to the host, processes the data “in situ” and sends the results back to the host.

Basically, CSD designers can disaggregate and move computing from the host to in situ to improve performance, lower power usage, and free up PCIe bandwidth for the rest of the system.

Several applications benefit from the CSD, including hyperscale data centers, image recognition, edge computing, AI/ML, real-time analytics, database query, and others.

Hardware Emulation for Storage

SSD and CSD traditional verification approaches were defeated by the non-deterministic nature of the storage. Emulation-based virtual verification offers new verification methods. Through virtualization, complete system verification including full firmware validation can be carried out at high speed to accelerate time to market and perform architectural explorations to create the optimal solution for a specific task. SSD virtualization allows for pre-silicon performance and latency testing within 5% of actual silicon.

Figure #5: Exhaustive CSD verification with emulation. (Image source: Siemens EDA)

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Power Trends and Power Analysis
Designing silicon with process nodes below 28nm magnifies the disadvantages of dynamic power consumption in several market segments including mobile and CPU/GPU, data centers, automotive, and AI/ML.

Accurate identification of peaks, valleys, and hotspots in pre-silicon designs are challenges for quick and efficient power analysis. Add overcoming long turnaround times, high disk consumption, and bulky formats for waveform generation like fast signal database (FSDB) and value change dump (VCD). Accurate and realistic results can only be achieved running real-world OS and industry benchmarks, such as 3DMark, GFXBench, Geekbench, AnTuTu, which mandate a high-performance engine and an integrated validation flow.

Hardware Emulation for Power Analysis
A modern hardware emulator can generate an activity plot early in the design verification cycle by running real-world applications before register transfer level (RTL) code availability to quickly find where and when hotspots and valleys are happening. It can determine what is causing the spikes within hardware hierarchies and produce a hotspot map that shows which IP or blocks are power hogs.

Once the hardware emulation platform identifies time windows in the design hierarchies, it can generate detailed switching information within those windows to feed a power analysis tool. This is typically done by creating a flat-file streaming database (FSDB) or in Switching Activity Interchange Format (SAIF) files. A better approach would be via a direct API access from the emulator to the power tool and bypass the file generation for a faster and more efficient procedure.

Once the power tool has the information, it can generate accurate power numbers to help to make changes to the RTL design to lower power consumption. After making the appropriate changes, a new verification cycle can validate the validity of those changes.

Figure #6: Complete power solution. (Image source: Siemens EDA)

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Summary
Market trends in data center networking, communication and 5G, autonomous driving, AI and ML, and storage positively impact the hardware-assisted verification landscape. Hardware-assisted verification is a mandatory investment as chips get larger, more complex with more interfaces, and hardware and software code integration become critical early in the design side. No other verification tool can meet these challenges.

About the Authors
— Jean-Marie Brunet is senior director of product management and engineering for emulation and prototyping at Siemens EDA. He has served for more than 20 years in application engineering, marketing and management roles in the EDA industry, and has held IC design and design management positions at STMicrolectronics, Cadence, and Micron, among others.

Lauro Rizzatti is a verification consultant and industry expert on hardware emulation. Previously, Rizzatti held positions in management, product marketing, technical marketing, and engineering.


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