IAR Systems®, the future-proof supplier of software tools and services for embedded development, announces the immediate availability of the leading C/C++ compiler and debugger toolchain IAR Embedded Workbench® with support for RISC-V cores.
Through excellent optimization technology, IAR Embedded Workbench helps developers ensure the application fits the required needs and optimize the utilization of on-board memory. This also enables companies to aggregate value by adding functionality to an existing platform. Internal tests show that the first version of the IAR C/C++ Compiler™ for RISC-V already delivers major improvements in code density, generating code that is considerably smaller compared to code generated by other available tools. To ensure code quality, the toolchain includes C-STAT® for integrated static code analysis. C-STAT can help prove compliance with specific standards like MISRA C:2004, MISRA C++:2008 and MISRA C:2012, as well as detect defects, bugs, and security vulnerabilities as defined by the Common Weakness Enumeration (CWE) and a subset of CERT C/C++.
The C-SPY® Debugger included with IAR Embedded Workbench gives full control of the application in real time, and its simulator provides full debugging capabilities even without access to the hardware. For in-circuit debugging, IAR Systems provides the probe I-jet™, delivering a high-speed debugging platform with full code control.
“RISC-V is turning into an important and broad architecture and many companies are adopting it in their designs,” says Stefan Skarin, CEO, IAR Systems. “These companies have a lot to gain by having access to professional development tools with professional technical support. As a commercial tools vendor, we have a unique position in the RISC-V ecosystem by being able to provide global technical support, as well as invest in stable technology, and we are now taking RISC-V development to the next level.”
“We are so excited to see IAR Systems offering a strong commercial tools alternative for RISC-V,” says Chunqiang Li, Senior Staff Engineer and VP, C-SKY/Alibaba. “There are a rapidly growing number of RISC-V based commercial products, and we are sure there will be a strong positive response in the market to IAR Systems’ leading code optimization technology as well as professional technical support. As a Platinum member of the RISC-V Foundation, we will continue to promote RISC-V evolution and cooperation in various technical directions such as ISA optimization, code density optimization, and security. Besides, we have also developed a series of CPU cores based on RISC-V, and we will expand cooperation with IAR Systems on the tools.”
“We are glad to see early support for our AndesCore processors in IAR Embedded Workbench,” comments Dr. Charlie Su, CTO and Executive VP, Andes Technology Corporation. “IAR Systems always delivers high-performance development tools as well as comprehensive debugging capabilities that will enable our customers to reduce time to market and create highly competitive embedded applications. We are really excited about this launch.”
“A member of our Mi-V ecosystem for implementing FPGA-based RISC-V designs, IAR Systems has a strong track record of delivering excellent performance and comprehensive services with their tools,” said Tim Morin, director of product marketing for the FPGA business unit at Microchip’s Microsemi subsidiary. “We are pleased to see them adding RISC-V coverage to their portfolio, and we will continue to work together to ensure optimized development for our joint customers.”
“I’m thrilled to see IAR Embedded Workbench for RISC-V join the robust tools available in the RISC-V ecosystem,” said Yunsup Lee, designer of the RISC-V ISA and Chief Technology Officer at SiFive. “High quality, commercially supported tools for SiFive devices are key to enabling the innovators who need customizable processors with dense, high-performance code to maximize their efforts.”
“The addition of IAR Embedded Workbench to the RISC-V ecosystem will further push the RISC-V adoption across the embedded industry.” says Calista Redmond, CEO, RISC-V Foundation. “IAR Systems provides development tools for users all over the world, and I’m excited to witness the company’s compiler technology, static code analysis and extensive debug functionality brought to the RISC-V community.”
RISC-V is a free and open instruction set architecture (ISA) based on established Reduced Instruction Set Computing (RISC) principles. In 2018, IAR Systems joined the non-profit RISC-V Foundation, which drives the adoption and implementation of the RISC-V ISA, and committed to bring its leading development tools to the growing RISC-V community. Complementing its strong tools product offering, IAR Systems delivers outstanding technical support from offices around the globe.
The first version of IAR Embedded Workbench for RISC-V provides support for RV32 32-bit RISC-V cores and extensions. Future releases will include 64-bit support and support for the smaller RV32E base instruction set, as well as functional safety certification and security solutions. Learn more at www.iar.com/riscv.