Xilinx Announces Integration of 56G PAM4 Transceiver Technology into its Virtex UltraScale+ FPGAs

Today announced integration of 56G PAM4 transceiver technology into its industry-leading Virtex® UltraScale+™ FPGAs. Built upon proven 16nm FinFET+ FPGA fabric, these devices will expand the Virtex product line to drive the next wave of Ethernet deployment and provide seamless migration of existing systems to next-gen backplane, optics, and high performance interconnects.

Targeted for wired communications, data centers, and wireless backhaul applications, the integrated devices enable customers to double bandwidth on existing infrastructure by breaking through the physical limitations of data transmission at 56G+ line rates.

“Xilinx is leading the charge on transceiver technology with the infusion of 56G PAM4 into our 16nm FPGAs,” said Ken Chang, vice president, SerDes Technology Group at Xilinx. “These new devices are built upon a proven FPGA foundation and are in alignment with the vast ecosystem of optics, ASICs, and backplanes soon to be deployed.”

Today’s announcement signals another milestone for Xilinx transceiver leadership after the company was first to demonstrate 56G PAM4 transceiver technology on a 16nm programmable device in 2016. View the Xilinx 56G PAM4 technology demo and contact your local sales representative for more information.