Lattice Opens Orders for Mach-N2 Secure-Control FPGAs with Post-Quantum Protection

The new Nexus 2-based family scales to 220,000 system logic cells, while a dedicated Root-of-Trust device adds field-updatable post-quantum cryptography. Lattice has also released an MCP server that connects AI development tools to its Radiant FPGA workflow.

Lattice Semiconductor has introduced the Mach-N2 family of secure-control FPGAs, extending its programmable system-management portfolio to higher logic densities and faster interfaces. The devices are available to order, and Lattice says samples have already been shipped to unnamed customers in the computing and communications sectors.

Built on the company’s Nexus 2 platform, the family spans five devices with between 65,000 and 220,000 system logic cells. The largest general-purpose member, the MH20, provides 220,000 cells, 12 Mbit of embedded memory and 520 18 × 18 multipliers. The security-focused MH21D provides 215,000 cells and 10.4 Mbit of embedded memory.

The distinction between the devices matters because Lattice’s post-quantum functions are associated with the MH21D Root-of-Trust variant rather than every member of the family. That device supports ML-KEM for key establishment and ML-DSA, LMS and XMSS for authentication. It also derives device identity from a physical unclonable function and supports DICE and SPDM attestation.

The security architecture is designed to remain updateable after deployment. Cryptographic algorithms can be replaced in the field, while anti-rollback protection is intended to prevent a system from being forced back to an older, vulnerable implementation. Classical protection includes AES-256-GCM bitstream encryption and ECDSA or RSA authentication.

Mach-N2 combines programmable logic with on-chip non-volatile flash for configuration and data storage. Keeping the configuration image inside the FPGA reduces exposure of the bitstream on an external memory interface and enables single-chip startup. Lattice specifies a configuration time below 30 ms for a 220,000-cell device and support for as many as three stored images: primary, secondary and a golden recovery image.

High-speed connectivity includes PCI Express 4.0, 10 Gigabit Ethernet and SerDes operating at up to 16 Gbit/s. Lattice is positioning the devices for always-on system functions such as power sequencing, platform monitoring, component authentication, secure boot supervision and management of servers, network equipment and industrial systems.

The company has not disclosed device pricing, power consumption, order lead times or the timetable for volume production. Those omissions are relevant because the launch establishes order availability and initial sampling, but not yet broad production deployment.

AI-assisted access to the FPGA toolchain

Alongside the hardware launch, Lattice released Lattice Prompt, a free Model Context Protocol server for the latest version of its Radiant design software. The tool allows compatible large-language-model assistants and agentic development environments to invoke stages of the FPGA workflow through natural-language requests.

According to Lattice, Prompt can interact with simulation, synthesis, mapping, placement and routing, timing analysis and bitstream generation, and can also produce design reports and documentation. It works with MCP-compatible environments including Claude Code, Cursor and Visual Studio Code.

Lattice says the software can improve productivity by ten times or more on common design tasks. That figure is a company claim and has not been supported by a published independent benchmark. The more concrete development is the use of an open MCP interface to connect AI tools with an established FPGA implementation flow, while keeping the generated output subject to the same compilation and timing checks used in a conventional Radiant project.

Sources:
Lattice Mach-N2 launch announcement
Lattice Mach-N2 product information
Lattice Prompt announcement

Credit: Lattice Semiconductor