Marvell Demonstrates 2 nm Optical DSPs for 400G-per-Lane and 1.6T Links

Marvell is demonstrating a group of optical-interconnect technologies manufactured at the 2 nm process node, covering 400 Gbit/s-per-lane

PAM4 transmission, secured 800G data-centre links and 1.6T coherent connections.

The demonstrations are taking place at ECOC 2026 in Málaga and extend Marvell’s optical DSP roadmap from previously announced devices into operating hardware. They address connections within AI clusters, between racks and across data-centre campuses.

For short-reach connectivity, Marvell is showing a 400 Gbit/s-per-lane optical PAM4 link. Increasing the line rate per optical lane is intended to enable future 3.2 Tbit/s interfaces without doubling the number of fibres, lasers and receiver channels used by current 1.6T modules.

Marvell is also demonstrating an 800G ZR/ZR+ OSFP pluggable based on its 2 nm Libra coherent DSP. The module integrates MACsec, providing link-layer encryption and authentication inside the optical connection rather than relying solely on external network equipment.

A third set of demonstrations covers 1.6T ZR and O-band coherent-lite transmission. ZR optics are designed for coherent links between data centres, while coherent-lite seeks to apply some coherent-processing techniques to shorter connections with lower complexity and power than a complete long-haul coherent implementation.

Separating demonstrations from products

The announcement combines several technologies at different stages of maturity. Libra and Marvell’s next-generation 1.6T DSPs were announced earlier in 2026. What is new at ECOC is the live operation of complete link configurations, rather than disclosure of the underlying roadmap alone.

Marvell is additionally showing a 102.4 Tbit/s co-packaged-optics platform using 200G-per-lane silicon photonics. In a CPO architecture, optical engines are placed adjacent to switch or accelerator silicon to shorten high-speed electrical traces and reduce the signal loss associated with conventional front-panel modules.

None of the demonstrations should automatically be treated as a commercially available product. Marvell has not published bit-error-rate measurements, optical reach, power per bit, DSP power, link budget, module temperature or the test conditions used during the demonstrations. It has also not provided sampling or production dates for the 400G-per-lane and 1.6T configurations.

The 2 nm process may improve logic density and energy efficiency in the digital signal processor, but the process node by itself does not establish the power or performance of the complete optical module.

Lasers, modulators, drivers, receivers, packaging and cooling all contribute to the system result.

The engineering significance therefore lies in the range of links operating around a common 2 nm DSP generation. The next commercial milestone will be measured specifications, interoperability results and hardware that customers can order for qualification.