Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its complete suite of digital and signoff tools has achieved certification for Samsung Foundry’s Process Design Kit (PDK) and foundation library for the 14LPP process. The Cadence® 14nm FinFET reference flow has been validated by Samsung using a quad-core design with the ARM® Cortex®-A53 processor, which was implemented with the low-power methodology covering power-gating, IEEE 1801 UPF2.0 power intent, memory retention and multibit-FF optimization.
The Cadence digital and signoff tools met all of Samsung’s accuracy requirements, providing customers with a faster path to implementation and closure, as well as optimal power, performance and area (PPA) on the 14LPP process. In addition, the Cadence signoff tools have been certified for tapeout against the Samsung certification criteria. The tools in the flow include:
For more information on the Cadence digital and signoff solutions, please visit www.cadence.com/news/samsung14nm.
“Samsung worked closely with Cadence to put a certified reference flow in place so our joint customers can reduce iterations and improve predictability when creating 14nm FinFET designs,” said Ben Suh, senior vice president of sales and marketing at Samsung Foundry. “The ease-of-use of the design flow and methodology enhances the value of our foundry capability and provides our customers with the ability to create high-value designs within tight market windows.”
“The certification of the Cadence tools ensures tight correlation and predictability, providing customers with confidence that 14nm FinFET designs work as intended,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group and the System Verification Group at Cadence. “Customers using the Cadence flow on the Samsung 14nm FinFET process can also achieve smaller area, higher performance and lower power-consumption benefits in addition to faster turnaround times.”
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