, Sweat-proof “smart skin” takes reliable vitals, even during workouts and spicy meals
, Sweat-proof “smart skin” takes reliable vitals, even during workouts and spicy meals

Happy 25th Birthday, Virtuoso!

There are a lot of changes going on in the environment in which analog design gets done. In the past, a lot of analog designs were relatively small designs in non-leading-edge processes. These chips would go into specialized markets such as automotive and medical. But these markets are changing dramatically. In automotive, advanced driver assist systems (ADAS) are a stepping stone on the way to fully autonomous vehicles. Medical systems are requiring increasing amounts of computation.

These trends, and similar ones in other industries, have a number of effects on analog design. First, instead of being small standalone designs, analog is increasingly moving to being a block on a mixed-signal SoC with a large amount of digital logic doing the computation and signal processing. In turn, this means that analog design needs to be done in more advanced processes such as 14/16nm FinFET or 22nm FD-SOI. In these processes, doing high-precision analog design is not really feasible and the optimal way to do analog design is to do a less precise solution and add a lot of digital logic to correct and tune the solution to take account of variability in the silicon.

virtuosoA big change is in analog verification, where instead of having to verify a standalone analog part, the analog verification needs to be part of verification of a much larger, possibly very large, mixed-signal SoC. But a bigger change is that these designs are parts of critical electronic systems with implications for human life. So, as the electronic content of critical systems increases, standards have been created on how these devices should be verified and tested. In automotive, the buzzword is ISO 26262, which is the functional safety standard. In aerospace it is DO-254, in industrial IEC 61508. In medical, there is a whole range of standards such as IEC 60601 and IEC 62304. To add to the complexity, the requirements for medical electronics are governed by different organizations in different countries: the FDA in the US, EMA in Europe, CFDA in China, and so on.

These reliability standards have a lot in common. In particular, they require traceability from requirements via verification tests, along with change management to handle the inevitable specification changes.

However, there is another big change in verification in these markets. While it is annoying if your cellphone crashes, that is not in the same league as your car’s anti-lock braking system crashing, or your heart-pacemaker rebooting. The first line of defense is ensuring that all the line items in the specification are linked to tests that pass (traceability), essentially ensuring that the system behaves well in normal operation. But that is not enough in these life-threatening situations. It is also necessary to ensure acceptable behavior in the face of failures due to single event effects (high-energy neutrons, etc.), failures of a transistor or a piece of interconnect, thermal overload, battery voltage droop, and so on. During normal operation, chips need to degrade gracefully and be able to detect failures and handle them in some non-life-threatening way. This all means that requirements need to be traceable, not just in the digital part of the SoC but in the analog blocks, too.

There are a number of approaches to crossing the verification chasm betweeen analog and digital. But the best approach is to maintain analog circuits and tests but track them along with the digital. And that is just what the new Virtuoso ADE Verifier tool does for you.

It is Virtuoso’s 25th anniversary. I think that must make it the oldest EDA product that you can still buy today. Of course it is very different from that original product, but it is still at heart a layout editor and it has always been called Virtuoso. I think it is the only remaining product from those early Cadence days when many products had names related to music (well, the Cadence name itself is related to music, of course). Virtuoso continues to develop and there are four new enhancements to the Virtuoso analog design environment (ADE) being announced today.

Virtuoso ADE Explorer: This highly interactive single testbench analyzer assists engineers in the earliest stages of circuit design. It includes Monte Carlo (MC) and corners analysis, and device tuning mode using Spectre circuit simulators, including checks and asserts assistant for detecting glitches.

Virtuoso ADE Assembler: This interactive, multi-testbench environment is designed to pull together all parts of the design and their various specs to begin centering the design for manufacturing. It includes local and global optimization algorithms to aid in design centering, capability to develop worst-case-corners from a defined corner set and to size device parameters over those corners, and design migration for moving designs between processes.

Virtuoso Variation Option: This option provides advanced statistical analysis for deeper circuit exploration, particularly at advanced nodes, fast MC yield verification with sample reodering (special foundry APIs available for 16nm and below), high yield estimation algorithm (>3σ), and statistical sensitivity and mismatch analyses.

Virtuoso ADE Verifier: For the first time, Virtuoso includes a circuit verification environment, with a regression environment for pulling together large final verification jobs. It sits above analog testbenches allowing for unique sequencing, and provides the bridge between the analog world and the more extensive and well-defined metric-drivern digital flows.

Also, designs are getting larger (well, duh!) so there has been a lot of performance enhancement, including a 10X-100X increase in zooming, panning, dragging, and drawing large layouts. Also, new ModGen interactive pattern manipulation to make real-time customization simple. Plus, enhanced structured device level routing (pin-to-trunk) algorithms enhance productivity by 1.5X.

So this is the next logical evolution in analog design:

  • Increased usability for engineers without being intrusive
  • Deep integration with Spectre, reducing the time to find errors by 50%
  • New faster graphics rendering engines improve navigating huge layouts by 10-100X
  • Enhanced routing improving productivity by 1.5X
  • Analog electric design verification integrated with requirements tracking

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