Switchtec™ Gen 6 PCIe Fanout Switches deliver extra bandwidth, low latency and advanced security for high-performance compute, cloud computing
and hyperscale data centers
As artificial intelligence (AI) workloads and high-performance computing (HPC) applications continue to drive unprecedented demand for faster data movement and lower latency, Microchip Technology (Nasdaq: MCHP) has introduced its next generation of Switchtec™ Gen 6 PCIe® Switches. The industry’s first PCIe Gen 6 switches manufactured using a 3 nm process, the Switchtec Gen 6 family is designed to deliver lower power consumption and support up to 160 lanes for high-density AI system connectivity. Advanced security features include a hardware root of trust and secure boot, utilizing post-quantum safe cryptography compliant with the Commercial National Security Algorithm Suite (CNSA) 2.0.
Previous PCIe generations created bandwidth bottlenecks as data transferred between CPUs, GPUs, memory and storage, leading to underutilization and wasted compute cycles. PCIe 6.0 doubles the bandwidth of PCIe 5.0 to 64 GT/s (giga transfers per second) per lane, providing the necessary data pipeline to keep the most powerful AI accelerators consistently supplied. Switchtec Gen 6 PCIe switches enable high-speed connectivity between CPUs, GPUs, SoCs, AI accelerators and storage devices, and are designed to help data center architects scale to the potential of next generation AI and cloud infrastructure.
“Rapid innovation in the AI era is prompting data center architectures to move away from traditional designs and shift to a model where components are organized as a pool of shared resources,” said Brian McCarson, corporate vice president of Microchip’s data center solutions business unit. “By expanding our proven Switchtec product line to PCIe 6.0, we’re enabling this transformation with technology that facilitates direct communication between critical compute resources and delivers the most powerful and energy efficient switch we’ve ever produced.”
By acting as a high-performance interconnect, the switches allow for simpler, more direct interfaces between GPUs in a server rack, which is crucial for reducing signal loss and maintaining the low latency required by AI fabrics. The PCIe 6.0 standard also introduces Flow Control Unit (FLIT) mode, a lightweight Forward Error Correction (FEC) system and dynamic resource allocation.
These changes make data transfer more efficient and reliable, especially for small packets which are common in AI workloads. These updates lead to higher overall throughput and lower effective latency.
Switchtec Gen 6 PCIe switches feature 20 ports and 10 stacks with each port featuring hot- and surprise-plug controllers. Switchtec also supports NTB (Non-Transparent Bridging) to connect and isolate multiple host domains and multicast for one-to-many data distribution within a single domain. The switches are designed with advanced error containment and comprehensive diagnostics and debug capabilities, a wide breadth of I/O interfaces and an integrated MIPS processor with bifurcation options at x8 and x16. Input and output reference clocks are based on PCIe stacks with four input clocks per stack. Visit the website to learn more about Microchip’s full portfolio of PCIe switches.
Development Tools
The Switchtec Gen 6 PCIe Switch family is supported by Microchip’s ChipLink diagnostic tools, offering comprehensive debug, diagnostics, configuration and analysis through an intuitive graphical user interface (GUI). ChipLink connects via in-band PCIe or sideband signals such as UART, TWI and EJTAG, enabling flexible, efficient monitoring and troubleshooting throughout design and deployment. The switches are also supported by the PM61160-KIT Switchtec Gen 6 PCIe Switch Evaluation Kit with multiple interfaces.
Pricing and Availability
Switchtec Gen 6 PCIe switches are available for sampling to qualified customers. Contact a Microchip sales representative or authorized worldwide distributor for more information.
Resources
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