Imperas Announces Partnership with Breker to Drive Rigorous Processor to System Level Verification for RISC-V

With a unified, standards-based approach to verification and Verification IP reusability, mutual customers can seamlessly transition between RISC-V processor and system level DV

Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced a partnership with Breker Verification Systems, a leading provider of advanced test content synthesis solutions for SoC, UVM and Post-Silicon verification environments.

With a combined approach to standards-based verification, development teams will be able to efficiently transition from RISC-V processor functional design verification (DV) right through to system level and SoC integration testing, including automated cache coherency validation.

With the new flexibility offered by the open, standard ISA (Instruction Set Architecture) of RISC-V, SoC developers can now optimize a custom processor for domain specific applications. However, the use of these new RISC-V cores introduces additional system level integration verification challenges.

Together, leveraging their proven expertise in processor simulation and system verification respectively, Imperas and Breker plan to develop interfaces and standards to unify the functional verification design flows to enable DV teams to improve efficiency and verification IP reuse across the complete verification process from plan to silicon prototype.

“RISC-V represents an inflection point for semiconductor verification as the design freedoms provided by the open ISA means an assumption of the responsibility of the processor and system verification task,” said David Kelf, CEO at Breker Verification Systems. “In partnering with Imperas, the leaders in RISC-V processor verification, we can offer a combination of technologies and interface standards for IP and SoC testing that ensures commercial grade verification for these flexible devices right through to the end platform.”

“RISC-V marks the end of the one-size-fits-all approach to processor IP, now all SoC developers can explore new innovations with processor IP configured for the target application,” said Simon Davidmann, CEO at Imperas Software Ltd. “Many of our customers are exploring the design side possibilities of new processor architectures and their implications for SoCs and systems in parallel, extending the verification scope from IP cores to system level integration. With Breker’s proven system verification experience, we are streamlining the critical verification tasks to enable the full potential of RISC-V based devices with commercial-grade verified quality.”

Imperas and Breker at the Design Automation Conference 2022 (DAC 59)

Imperas and Breker will participate at DAC, July 10-14 in San Francisco, California. Please stop by and see the latest developments for RISC-V Verification, see Breker at booth #2528 and Imperas at booths #2336 and also in the OpenHW pavilion at #2340 https://www.dac.com