Taking the Risk Out of SW-Driven Networking SoCs

The massive adoption of software-driven networking (SDN) architectures has been driven by the upsurge of new markets such as cloud computing, big datacenters, and mobile. In turn, SDN dramatically pushes design complexity, size, and port counts to new heights, posing several challenges to stressed-out design teams developing one of these monster SoCs.

These challenges cannot be addressed by traditional software-based simulation tools, nor by formal tools. In the billion-gate arena, only hardware-driven verification engines can accomplish these challenging tasks, meet a tight schedule and avoid fatal delays that may wipe out potential revenues in the fast moving networking market.

Among the hardware-based verification engines, hardware emulation has emerged as the best tool for pre-silicon verification. A modern emulator provides virtually unlimited capacity to emulate the largest designs, offers total design visibility and access/control without instrumentation/compilation and supports high throughput, along with fast, predictable compile and bring-up time. It can accommodate multiple concurrent users with optimum utilization of resources. It can be deployed in several modes of operation to perform a multitude of verification tasks.

When it comes to verifying a networking SoC design with many ports, design teams are moving from a traditional in-circuit emulation (ICE) setup to a virtual test environment, eliminating any hardware and, with that, all hardware dependencies, including noise, power, cables, reliability and associated costs. Virtual devices can be built before availability of actual hardware by using a combination of software and synthesizable hardware models, which facilitates easy reconfigured through this software. They run at emulation speed, support multi-users and multi projects, are accessed remotely and deployed in datacenters.

The virtual mode, however, requires the creation of a virtual test environment, a non-trivial task. In this regard, Mentor Graphics took the lead and developed a comprehensive and sophisticated virtual environment, called VirtuaLAB, to support pre-silicon testing of application-specific SoC designs. For networking designs, VirtuaLAB includes an Ethernet Packet Generator and Monitor (EPGM) that generates, transmits and monitors Ethernet packets to/from the design under test (DUT). It has the ability to configure25GMII, 50GMII, 200GMII, 400GMII.

Each VirtuaLAB supports up to 32 ports. Multiple VirtuaLAB systems can be assembled to expand the port count to greater than 1000. Figure 3 compares an ICE setup versus an equivalent VirtuaLAB for testing a 128-port Ethernet switch.

As powerful as a VirtuaLAB for pre-silicon verification can be, when applied to post-silicon testing of engineering samples in the lab, its effectiveness is encumbered. Instead, the methodology for testing networking engineering samples in the lab is through the use of dedicated hardware networking testers.

Under this scenario, the verification landscape shows two gaps. The first is a gap between simulation and emulation. The second gap is between pre-silicon verification, based on hardware emulation and VirtuaLAB performed in a design center, and post-silicon testing performed by specialized testers in a lab.

Once more taking the lead, Mentor Graphics spearheaded an initiative to fill the gap between  the emulation environment and the lab. It entered into an agreement with IXIA, worldwide leading provider of comprehensive solutions for testing of network equipment and network applications. IXIA products cover the entire spectrum of networking testing needs, from performance, to functional, to security and conformance testing, including physical testers and virtual testers.

Continuing to expand the catalog of Veloce Emulation Platform Apps, Mentor and IXIA jointly developed an integration between IXIA’s IxNetwork® Virtual Edition (VE) test product family as the emulation test front-end with a new Mentor Veloce Virtual Network (VN) App as the back-end. The front-end, called IxVerify is based on IXIA’s IxNetworkVE test products, uses the same GUI and enables reuse of test scripts and functionality. In fact, the customer experience is undifferentiated from what IXIA customer observe today.

VN App serves as the back-end and includes a Veloce Flow Control mechanism running on the workstation and a transactor mapped inside the Veloce emulator, creating a high-performance optimized dataplane flow from an IXIA test platform to emulation. The overall solution fills the gap between simulation, emulation and the lab for greater efficiency and improved debug.

The partnership between Mentor Graphics and IXIA offers networking customers the ability to seamlessly integrate an IXIA virtual environment into an emulation-based verification flow, bringing the powerful advantages of emulation to the lab environment. This allows the reuse of traffic flow generation scripts for greater efficiency and improved debug, faster time-to-market, and gives design teams the ability to de-risk the challenges of complex chip designs.

A real shift-left in pre-silicon verification using a post-silicon software development kit (SDK) and test environment is finally within reach. De-risking complex networking SoC development is not a remote objective anymore. Rather it is available to all design teams today.