Achronix Announces Immediate Availability of Speedcore Embedded FPGA IP for SoC Acceleration

Speedcore embedded FPGAs improve throughput and latency performance by 10X, reduce power by 50 percent and reduce cost by 90 percent
Speedcore shipping to customers today
Santa Clara, Calif., October 11, 2016 – Achronix today announced the immediate availability of its Speedcore™ embedded FPGA (eFPGA) IP for integration into customers’ SoCs. Speedcore is designed for compute and network acceleration applications and is based on the same high-performance architecture that is in Achronix’s Speedster 22i FPGAs that have been shipping in production since 2013. Speedcore eFPGA products are fully supported by Achronix’s robust and proven ACE design tools.

With Speedcore, customers specify the optimal die size, power consumption and resource configuration required for their end application. Customers define the quantity of look-up-tables (LUTs), embedded memory blocks and DSP blocks. Additionally customers define the Speedcore aspect ratio, IO port connections and can make tradeoffs between power and performance. Achronix delivers a GDS II of the Speedcore IP that customers integrate directly into their SoC, and a custom, full-featured version of the ACE design tools that customers use to design, verify and program the functionality of the Speedcore eFPGA.

“Over the years, different companies have talked about eFPGA products, but Achronix Speedcore is the first eFPGA IP to ship to end customers, and it is a game changer” said Robert Blake, President and CEO, Achronix Semiconductor. “Achronix was the first company to deliver high density FPGAs with embedded system level IP. We are using that same proven methodology to deliver our eFPGA technology to customers who want to combine all the efficiencies of ASIC design with the flexibility of eFPGA programmable hardware accelerators on the same chip.”

“Designers have long sought the inherent advantages that could come from embedding FPGA functionality as IP into SoCs for a host of different high performance applications,” said Richard Wawrzyniak, Principal Analyst for ASIC & SoC at Semico Research Corp. “Achronix has now delivered eFPGA IP to customers who are developing high-performance computing products where offloading compute intensive functions from processors to FPGA IP can provide a tremendous performance boost. While an exciting opportunity for Achronix, seeing FPGA IP become a reality is great news for the semiconductor industry, particularly when you consider the large market opportunity for compute high-performance applications.

Speedcore is the Optimal Hardware Accelerator
Compute and communications infrastructure in data centers and enterprises can no longer keep pace with exponential data growth rates, changing security and software virtualization requirements. Traditional multi-core CPUs and SoCs need programmable hardware accelerators that pre-process and offload data to increase their compute performance. FPGAs are the optimal hardware accelerator solution because accelerators need to be updated with new functionality as algorithms are constantly changing. Standalone FPGAs are a convenient and practical solution for low to medium volume applications, whereas Speedcore is the optimal solution for high volume applications and offers significant advantages:

Lower power:
Speedcore has direct wire connections to the SoC, which eliminates the large programmable IO buffers found in standalone FPGAs. Programmable IO circuitry accounts for half of the total power consumption of standalone FPGAs.
Speedcore is sized exactly to the requirements of the customer’s end application
Customers can tune the process technology to tradeoff performance for lower power
Higher interface performance:
Speedcore offers dramatically higher interface performance than standalone FPGAs in the form of lower latency. Speedcore is connected to the ASIC through an ultra wide parallel interface whereas standalone FPGAs typically connect through a high latency SerDes structure.
Lower system cost:
Speedcore die size is much smaller than standalone FPGAs because the programmable IO buffer structure is eliminated.
FPGAs have high pin counts which dictate the PCB layer count to support the FPGA BGA package escape routing. Additionally, Speedcore eliminates the need for all of the support components around the standalone FPGA including power regulators, clock generators, level shifters, passive components and FPGA cooling.
Higher system reliability and yields:
Integrating FPGA functionality into an ASIC improves system level signal integrity and eliminates reliability and yield loss associated with having a standalone FPGA on the PCB.
Process Technology
Speedcore is architected in modular fashion to support flexibility for customers to define their resource requirements and for Achronix to rapidly configure the Speedcore IP for delivery. Additionally, the modular architecture allows Achronix to easily port the technology to different process technologies and metal stacks. Speedcore is now available on TSMC 16FF+ and is in development on TSMC 7nm.

Easy to Evaluate Speedcore
Achronix’s ACE design tools include an example instance of Speedcore where customers can compile their designs today to evaluate Speedcore quality-of-results for performance, resource usage and compile times. Additionally Achronix has complete documentation on Speedcore functionality and ASIC integration methodologies. Customers interested in receiving die size and power information can contact Achronix for details on their specific Speedcore size and process.

Product Availability
Speedcore is now broadly available. Prior to this announcement, all information and customer discussions related to Speedcore were confidential. During the period of confidentiality, Achronix closed multiple Speedcore design. With this announcement, interested companies can get comprehensive information for these products at www.achronix.com/Speedcore.