NANIUM and UTAC Collaborate On Turnkey Backend Solutions for Wafer Level Packaging and Testing

a Portugal-based semiconductor manufacturing, test and engineering services provider and UTAC Holdings Ltd (UTAC), a Singapore-based semiconductor assembly and test services provider, signed a collaborative agreement to provide a complete turnkey backend solution for Wafer Level Packaging (WLP) solutions.

The collaboration will enable NANIUM and UTAC to offer customers a full turnkey solution comprising of NANIUM’s full suite of Wafer Level Packaging / Bumping Services including both Fan-in (WLCSP) and Fan-out (FOWLP) single chip, multi-chip or SIP wafer level processing, complemented by UTAC’s backend assembly and test services.

“NANIUM is an industry leader in WLP with an extensive track record and IP portfolio in Wafer Level Packaging / Bumping Services. Through this collaboration, we will be able to offer joint customers a seamless solution comprising NANIUM’s superior solutions and UTAC’s assembly and test capabilities spread across a wide manufacturing base in Asia,” said Mr. Asif Chowdhury, UTAC Senior Vice President of Product Line & Marketing.

“UTAC has well proven test capabilities and test engineering expertise coupled with a strong base of more than 1600 test platforms available in Asia. This collaboration will allow NANIUM to offer full turnkey WLP / Bumping Services to its customers worldwide, combining NANIUM’s WLP expertise with UTAC´s strong Test know-how and capacity.” said Mr. Paulo Queiroz, NANIUM’s Management Board Member.

The demand for wafer level processing remains strong in the analog, digital and logic areas, and is being more widely adopted by CMOS image sensor and MEMS devices. According to research house Yole Development (2015), the overall WLP market is projected to grow at a compound average growth rate of 9%, and the FOWLP (a subset) is predicted to have a 30% compound average growth rate 2016 to 2020.