Silicon Labs Significantly Reduces Design Time Using the Cadence Mixed-Signal Low-Power Flow

Cadence technology enables Silicon Labs to accelerate delivery of energy-efficient Blue Gecko Bluetooth Smart SoCs to the IoT market

Cadence Design Systems, Inc. (NASDAQ: CDNS) announced that Silicon Labs (www.silabs.com) used a Cadence® mixed-signal low-power flow to reduce overall design time, significantly speeding time to market. Silicon Labs adopted the flow for its new Blue Gecko family of wireless system-on-chip (SoC) devices (www.silabs.com/BlueGecko) that provide ultra-low-power Bluetooth Smart connectivity for Internet of Things (IoT) applications.

For design, Silicon Labs used the comprehensive Cadence mixed-signal, low-power flow based on the unified OpenAccess (OA)-enabled Incremental Technology Database (ITDB) to seamlessly interoperate between the Cadence Virtuoso® analog platform and the Cadence digital implementation suite of tools. For mixed-signal verification, Silicon Labs adopted the Cadence Spectre® Multi-Mode Simulation (MMSIM) solution, which improved productivity by up to 3X, helped reduce power consumption and extended the connectivity range of the Blue Gecko SoCs with high performance. The mixed-mode, full-chip functional simulation enabled by Incisive® Enterprise Simulator with its DMS Option accelerated Silicon Labs’ design verification by up to 10X, compared to transistor- or device-level simulation options.

For more information on the Cadence mixed-signal low-power flow, please visitwww.cadence.com/news/mixedsignal.

“Providing our IoT customers with the highest power output at the highest energy efficiency in a cost-effective manner is integral to the success of our wireless SoC products,” said James Stansberry, senior vice president and general manager of Internet of Things products at Silicon Labs. “Silicon Labs’ new Blue Gecko family of wireless SoC devices is designed to provide the performance, energy efficiency, security and design simplicity that Bluetooth Smart applications require, and the Cadence mixed-signal low-power flow helped us achieve our SoC product development and time-to-market goals.”

Silicon Labs used the Cadence Virtuoso analog platform, which included the Virtuoso Schematic Editor, the Virtuoso Analog Design Environment and the Virtuoso Layout Suite. The digital implementation suite consisted of the Innovus™ Implementation System, the Genus™ Synthesis Solution and Conformal® Low Power. The flow also incorporated Cadence signoff solutions—the Tempus™ Timing Signoff Solution, the Quantus™ QRC Extraction Solution, the Voltus™ IC Power Integrity Solution and the Voltus-Fi Custom Power Integrity Solution—to ensure first-pass silicon.

The Spectre MMSIM solution used by Silicon Labs consisted of the Spectre Classic Simulator, Spectre Accelerated Parallel Simulator (APS), Spectre RF Option and Virtuoso AMS Designer tool suites that provide comprehensive analog, RF and mixed-signal simulation capabilities to consistently, accurately and quickly design, verify and characterize complex wireless SoCs at both the block and chip levels.