Cadence Tempus Timing Signoff Solution Surpasses 200 Tapeout Milestone Within Two Years of Product Inception

Highlights:

• Solution becomes the most rapidly adopted signoff tool in Cadence history
• Production deployment across mature process nodes and advanced FinFET nodes
• Customers experience 5-10X faster signoff timing closure and significant PPA gains

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its customers have completed more than 200 tapeouts using the Tempus™ Timing Signoff Solution. Since its introduction in the fall of 2013, nearly 100 customers have rapidly deployed the solution on a wide range of production designs, from mixed-signal chips to high-speed processor cores to large 100M+-instance systems on chip (SoCs), across mature process nodes and advanced FinFET nodes. Customers have significantly benefited from the 5-10X faster signoff timing closure and significant power, performance and area (PPA) gains.

The Cadence® Tempus Timing Signoff Solution includes massively parallelized computation and physically aware timing optimization capabilities that enable designers to reduce time to signoff closure by significantly reducing engineering change order (ECO) iterations by an order of magnitude. Using the multi-threaded and distributable path-based analysis (PBA) capability, customers can also analyze thousands of critical paths in their design in a matter of minutes while eliminating hundreds of pessimistic violations reported otherwise by traditional static timing-analysis methods. The tool’s unique physically aware surgical timing optimization enables significant PPA gains in addition to any gains achieved using design implementation tools. Finally, customers have realized full-chip signoff accuracy within 1.5 percent of SPICE through multiple foundry certifications and qualifications.

“The Tempus Timing Signoff Solution is the most rapidly adopted signoff tool in Cadence history, and our customers have reached production use in a wide variety of applications, including Internet of Things (IoT), communications, computing, integrated radio frequency (RF) and mixed-signal ICs,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. “Customers using the Tempus Timing Signoff Solution have observed significant productivity gains, achieving faster runtimes and reductions in ECO loops so they can get their designs to market faster.”

The Tempus Timing Signoff Solution is a silicon-accurate, color-aware timing signoff and signal integrity analysis tool that supports advanced-node design requirements for waveform propagation, Miller Effect, ultra-low power, and variation associated with multi-patterning technologies. For more information on the Tempus Timing Signoff Solution, please visit www.cadence.com/news/tempus.